Processor core communication in multi-core processor
US8549339B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2010 |
| Grant date | Oct 1, 2013 |
| Priority date | — |
| Expiry date | Aug 4, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the disclosure generally set forth techniques for handling communication between processor cores. Some example multi-core processors include a first set of processor cores in a first region of the multi-core processor configured to dynamically receive a first supply voltage and a first clock signal, a second set of processor cores in a second region of the multi-core processor configured to dynamically receive a second supply voltage and a second clock signal, and an interface block coupled to the first set of processor cores and the second set of processor cores, wherein the interface block is configured to facilitate communications between the first set of processor cores and the second set of processor cores.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.