Framework for generating mixed-mode operations in loop-level simdization
US8549501B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2004 |
| Grant date | Oct 1, 2013 |
| Priority date | — |
| Expiry date | Mar 29, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/4452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Generating mixed-mode operations in the compilation of program code for processors having vector or SIMD processing units is disclosed. In a preferred embodiment of the present invention, program instructions making up the body of a loop are abstracted into virtual vector instructions. These virtual vector instructions are treated, for initial code optimization purposes, as vector instructions (i.e., instructions written for the vector unit). The virtual vector instructions are eventually expanded into native code for the target processor, at which time a determination is made for each virtual vector instruction as to whether to expand the virtual vector instruction into native vector instructions, into native scalar instructions, into calls to pre-defined library functions, or into a combination of these. A cost model is used to determine the optimal choice of expansion based on hardware/software constraints, performance costs/benefits, and other criteria.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.