Fabricating process of circuit substrate
US8549745B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 10, 2010 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | Nov 29, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A process for fabricating process a circuit substrate having a base layer, a first patterned conductive layer, a dielectric layer, a conductive block and a second patterned conductive layer. The first patterned conductive layer is disposed on the base layer and has a first pad. The dielectric layer is disposed on the base layer and covers the first patterned conductive layer, wherein the dielectric layer has an opening and the first pad is exposed by the opening. The conductive block is disposed in the opening and covers the first pad. The second patterned conductive layer is disposed on a surface of the dielectric layer and has a second pad, wherein the second pad and the conductive block are integrally formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.