Double gate planar field effect transistors

US8551833B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Josephine B. Chang · Mahopac, US
• Leland Chang · New York, US
• Chung-Hsun Lin · White Plains, US
• Jeffrey W. Sleight · Ridgefield, US

Key dates

• Filing date: Jun 15, 2011
• Grant date: Oct 8, 2013
• Expiry date: Oct 14, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

A stacked planar device and method for forming the same is shown that includes forming, on a substrate, a stack of layers having alternating sacrificial and channel layers, patterning the stack such that sides of the stack include exposed surfaces of the sacrificial and channel layers, forming a dummy gate structure over a region of the stack to establish a planar area, forming a dielectric layer around the dummy gate structure to cover areas adjacent to the planar area, removing the dummy gate structure to expose the stack, selectively etching the stack to remove the sacrificial layers from the channel layers in the planar area, and forming a gate conductor over and in between the channel layers to form a transistor device.