CMP process for processing STI on two distinct silicon planes

US8551886B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Kyle P. Hunt · Dallas, US
• Leila Elvira Noriega · Forney, US
• Billy Alan Wofford · Dallas, US
• Asadd M. Hosein · Plano, US
• Binghua Hu · Plano, US
• Xinfen Chen · Plano, US

Key dates

• Filing date: Apr 9, 2008
• Grant date: Oct 8, 2013
• Expiry date: Jan 5, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/31056
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for semiconductor processing is provided wherein a workpiece having an underlying body and a plurality of features extending therefrom, is provided. A first set of the plurality of features extend from the underlying body to a first plane, and a second set of the plurality features extend from the underlying body to a second plane. A protection layer overlies each of the plurality of features and an isolation layer overlies the underlying body and protection layer, wherein the isolation has a non-uniform first oxide density associated therewith. The isolation layer anisotropically etched based on a predetermined pattern, and then isotropically etched, wherein a second oxide density of the isolation layer is substantially uniform across the workpiece. The predetermined pattern is based, at least in part, on a desired oxide density, a location and extension of the plurality of features to the first and second planes.