Structure for CMOS ETSOI with multiple threshold voltages and active well bias capability

US8552500B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Robert H. Dennard · Croton-on-Hudson, US
• Terence B. Hook · Jericho, US

Key dates

• Filing date: May 24, 2011
• Grant date: Oct 8, 2013
• Expiry date: May 24, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A semiconductor substrate having a first type of conductivity and a top surface, a layer of oxide disposed over the top surface and a semiconductor layer disposed over the layer of oxide. A plurality of transistor devices are disposed upon the semiconductor layer. Each transistor device includes a channel between a source and a drain, where some transistor devices have a first type of channel conductivity and the remaining transistor devices have a second type of channel conductivity. A well region is formed adjacent to the top surface. The well region has a second type of conductivity. First trench isolation regions are between adjacent transistor devices that extend through the semiconductor layer. Second trench isolation regions are between adjacent transistor devices of opposite channel conductivity.