Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer
US8552508B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2010 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | Jul 7, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/987
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Gate electrodes are formed from conductive features that are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The gate electrodes include gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. Widths of the first and second p-type diffusion regions are substantially equal, such that the first and second PMOS transistor devices have substantially equal widths. Widths of the first and second n-type diffusion regions are substantially equal, such that the first and second NMOS transistor devices have substantially equal widths. The first and second PMOS and first and second NMOS transistor devices form a cross-coupled transistor configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.