Carole Lambert
54Patents
15h-index
11Co-inventors
77Inventor score
Filing activity: Jan 30, 2009 → Mar 11, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8863063B2 | Finfet transistor circuit | Emerging Cross-Sectional Technologies | 109 | Active |
| US8448102B2 | Optimizing layout of irregular structures in regular layout context | Emerging Cross-Sectional Technologies | 103 | Active |
| US8453094B2 | Enforcement of semiconductor structure regularity for localized transistors and interconnect | Emerging Cross-Sectional Technologies | 93 | Active |
| US8395224B2 | Linear gate level cross-coupled transistor device with non-overlapping PMOS transistors and non-overlapping NMOS transistors relative to directions of gate electrodes | Electricity | 87 | Active |
| US8405163B2 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature | Electricity | 81 | Active |
| US8575706B2 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level features inner extensions beyond gate electrode | Electricity | 75 | Active |
| US8847329B2 | Cross-coupled transistor circuit defined having diffusion regions of common node on opposing sides of same gate electrode track with at least two non-inner positioned gate contacts | Electricity | 61 | Active |
| US8701071B2 | Enforcement of semiconductor structure regularity for localized transistors and interconnect | Emerging Cross-Sectional Technologies | 60 | Active |
| US8836045B2 | Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track | Electricity | 56 | Active |
| US8735995B2 | Cross-coupled transistor circuit defined on three gate electrode tracks with diffusion regions of common node on opposing sides of same gate electrode track | Electricity | 56 | Active |
| US9202779B2 | Enforcement of semiconductor structure regularity for localized transistors and interconnect | Emerging Cross-Sectional Technologies | 41 | Active |
| US9009641B2 | Circuits with linear finfet structures | Emerging Cross-Sectional Technologies | 26 | Active |
| US8866197B2 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through another transistor forming gate level feature | Electricity | 20 | Active |
| US8569841B2 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least one gate level feature extending into adjacent gate level feature layout channel | Electricity | 15 | Active |
| US8729606B2 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels | Electricity | 15 | Active |
| US8853794B2 | Integrated circuit within semiconductor chip including cross-coupled transistor configuration | Electricity | 14 | Active |
| US8552508B2 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer | Electricity | 7 | Active |
| US8735944B2 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with serially connected transistors | Electricity | 7 | Active |
| US8872283B2 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature | Electricity | 6 | Active |
| US9213792B2 | Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods | Electricity | 6 | Active |
| US9754878B2 | Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires | Emerging Cross-Sectional Technologies | 5 | Active |
| US8816402B2 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate level feature layout channel including single transistor | Electricity | 5 | Active |
| US8847331B2 | Semiconductor chip including region having cross-coupled transistor configuration with offset electrical connection areas on gate electrode forming conductive structures and at least two different inner extension distances of gate electrode forming conductive structures | Electricity | 5 | Active |
| US8552509B2 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with other transistors positioned between cross-coupled transistors | Electricity | 5 | Active |
| US8592872B2 | Integrated circuit including cross-coupled transistors with two transistors of different type having gate electrodes formed by common gate level feature with shared diffusion regions on opposite sides of common gate level feature | Electricity | 4 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.