Mask making with error recognition
US8555211B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2012 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | Mar 9, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/36
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of making a mask includes receiving an IC design layout from a designer, applying an logic operation (LOP) correction, performing an OPC correction, fracturing the modified data into a plurality of main features in an electron beam format, and sending the electron beam format data to a mask writer for a mask fabrication. An XOR operation is implemented into the method to check and verify if a pattern is lost during OPC modification and/or data fracture. A BACKBONE XOR operation is also implemented into the method for a plurality of main features with a critical dimension (CD) size smaller than the max OPC correction to check and verify if a small pattern feature is lost during OPC modification and/or data fracture for 45 nm and beyond semiconductor technologies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.