Parallel solving of layout optimization
US8555229B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2011 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | Aug 4, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Solutions for optimizing an integrated circuit layout for implementation in an integrated circuit are disclosed. In one embodiment, a computer-implemented method is disclosed including: obtaining a plurality of hierarchical constraints in mathematical form, the plurality of hierarchical constraints defining a first integrated circuit layout; partitioning the plurality of hierarchical constraints into groups according to one or more partitioning rules; determining whether a boundary condition exists between two of the groups, and distributing a slack or a gap between the two of the groups in the case that the boundary condition exists; creating a plurality of integer linear programming problems associated with each of the groups; determining a solution for each of the plurality of integer linear programming problems; and integrating each solution together to form a second integrated circuit layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.