Method for fabrication of a semiconductor device and structure
US8557632B1 · kind B1 · utility
29Cited by
320References
30Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 9, 2012 |
| Grant date | Oct 15, 2013 |
| Priority date | — |
| Expiry date | May 31, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/401
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.