Three-dimensional integrated circuit (3DIC) formation process
US8557684B2 · kind B2 · utility
7Cited by
51References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2011 |
| Grant date | Oct 15, 2013 |
| Priority date | — |
| Expiry date | Aug 23, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P80/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes performing a laser grooving to remove a dielectric material in a wafer to form a trench, wherein the trench extends from a top surface of the wafer to stop at an intermediate level between the top surface and a bottom surface of the wafer. The trench is in a scribe line between two neighboring chips in the wafer. A polymer is filled into the trench and then cured. After the step of curing the polymer, a die saw is performed to separate the two neighboring chips, wherein a kerf line of the die saw cuts through a portion of the polymer filled in the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.