Integrated circuit packaging system with interposer interconnections and method of manufacture thereof
US8558366B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2011 |
| Grant date | Oct 15, 2013 |
| Priority date | — |
| Expiry date | Dec 28, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit; mounting a routing structure having a functional side above the integrated circuit; mounting a vertical interconnect to the functional side of the routing structure and the vertical interconnect extending vertically away from the routing structure; forming an encapsulation covering the integrated circuit, the routing structure, and sides of the vertical interconnect above the routing structure, and leaves a surface of the routing structure exposed from the encapsulation, and a portion of the vertical interconnect exposed from the encapsulation above the surface of the routing structure; mounting a first-external-package-component to the routing structure; and forming a first-external-package-encapsulation covering the first-external-package-component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.