Semiconductor packages and methods of fabricating the same
US8558400B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2011 |
| Grant date | Oct 15, 2013 |
| Priority date | — |
| Expiry date | Aug 5, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18301
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a wiring board including an upper connection pad provided on a first surface and a lower connection pad provided on a second surface opposite to the first surface, a semiconductor chip having a bonding pad area in which a bonding pad is provided and an adhesive area except the bonding pad area, and being mounted on the first surface of the wiring board in a flip-chip manner such that the bonding pad is electrically connected to the upper connection pad, a first molding layer provided between the adhesive area of the semiconductor chip and the first surface of the wiring board, and a second molding layer provided between the bonding pad area of the semiconductor chip and the first area of the wiring board while covering the first surface of the wiring board and the semiconductor chip. The first molding layer has a lower modulus than the second molding layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.