Dynamic level shifter for interfacing signals referenced to different power supply domains
US8559247B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 16, 2011 |
| Grant date | Oct 15, 2013 |
| Priority date | — |
| Expiry date | Apr 24, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic level shifter is disclosed. In one embodiment, a dynamic level shifter circuit may receive an input signal referenced to a first voltage of a first power domain, and may output a corresponding signal referenced to a second voltage into a second power domain. The dynamic level shifter circuit may include an evaluation node that is precharged during a first phase (e.g., the low portion) of a clock signal. During the second phase (e.g., the high portion) of the clock signal, the evaluation node may be either pulled low or high, depending on the state of the input signal. A corresponding output signal, based on the evaluated level on the evaluation node, may be output into the second power domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.