Method and apparatus for an automated input/output buffer information specification model generator
US8560294B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2008 |
| Grant date | Oct 15, 2013 |
| Priority date | — |
| Expiry date | Jul 31, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for automating input/output buffer information specification (IBIS) model generation. A wrapper utility combines components into an automated generation flow to model multiple input/output (I/O) buffers that conform to single-ended and differential I/O standards. Configuration data files are imported to properly configure the modeled I/O buffers according to a specific set of signal parameters across all process corners. Output and input termination impedance may also be modeled within the I/O buffer. A simulation setup file of the modeled I/O buffer is generated to determine the voltage/current (V/I) and voltage/time (V/T) data for the modeled I/O buffer for each process corner. A raw IBIS model is then created, formatted, and validated to determine the accuracy of the IBIS model. Execution steps of the IBIS model generator are then iterated to automatically generate, correlate, and compile IBIS models for each I/O standard into a single file.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.