Safe memory storage by internal operation verification

US8560899B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Simon Brewerton · Trowbridge, GB
• Neil Hastie · Gloucester, GB
• Paul Hubbert · Bristol, GB
• Klaus Oberlaender · San Jose, US
• Robert Wiesner · Chandler, US
• Antonio Vilela · Mering, DE
• Alfred Eder · Friedberg, DE
• Glenn Ashley Farrall · Long Ashton, GB

Key dates

• Filing date: Jul 30, 2010
• Grant date: Oct 15, 2013
• Expiry date: Oct 4, 2031

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2029/0411
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous.