Low power retention random access memory with error correction on wake-up
US8560931B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2012 |
| Grant date | Oct 15, 2013 |
| Priority date | — |
| Expiry date | Jul 12, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Solid-state random access memory including error correction capability applied to memory arrays entering and exiting a data retention mode. Error correction coding of the data to be retained is performed upon determining that a portion of the memory is to enter data retention mode; the parity bits (i.e., bits in addition to those required for storage of the payload) are stored in available memory cells within or external to the retention domain. Upon exit from retention mode, the code words are decoded to correct any errors, and the payload data are returned to the original cells. Error correction encoding and decoding is not performed in the normal operating mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.