Method of managing electro migration in logic designs and design structure thereof
US8560990B2 · kind B2 · utility
3Cited by
5References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2010 |
| Grant date | Oct 15, 2013 |
| Priority date | — |
| Expiry date | Nov 14, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of designing an integrated circuit includes modifying a design attribute-variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in order to avoid EM violations of an integrated circuit. The method further includes synthesizing the integrated circuit from a high level description to at least a subset of the pre-defined circuit devices using the modified design-variable EM limit of each pre-defined circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.