Method for inspecting a chip layout
US8560992B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2012 |
| Grant date | Oct 15, 2013 |
| Priority date | — |
| Expiry date | Nov 27, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for inspecting a chip layout. The method includes providing a chip layout having a plurality of patterns designed according to a design rule and performing a first inspection to the plurality of patterns according to the design rule. The method also includes determining patterns violating the design rule, as violating patterns, and corresponding violation values, and determining violating patterns having a minimum violation value among the violating patterns. Further, the method includes classifying the violating patterns having the minimum violation value into at least one sub-category based on characteristics of the violating patterns having the minimum violation value, and performing a second inspection on a selected violating pattern from the sub-category to determine whether the selected violating pattern and other violating patterns in the sub-category satisfy fabrication process conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.