Patent · US Active

Integrated circuit method with triple patterning

US8562843B2 · kind B2 · utility

1Cited by

2References

21Claims

0Family size

Assignee

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

Chia-Chu Liu · Taipei, TW
Kuei-Shun Chen · Baoshan, TW
Meng-Wei Chen · Taichung, TW

Key dates

Filing date	Oct 18, 2011
Grant date	Oct 22, 2013
Priority date	—
Expiry date	Feb 9, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH10D89/10
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of IC features. The method includes identifying, from the IC design layout, simple features as a first layout wherein the first layout does not violate design rules; and complex features as a second layout wherein the second layout violates the design rules. The method further includes generating a third layout and a fourth layout from the second layout wherein the third layout includes the complex features and connecting features to meet the design rules and the fourth layout includes trimming features.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.