Wafer level image sensor packaging structure and manufacturing method for the same
US8563350B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2010 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Aug 28, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F77/50
Abstract
The present invention discloses a wafer level image sensor packaging structure and a manufacturing method for the same. The manufacturing method includes the following steps: providing a silicon wafer with image sensor chips, providing a plurality of transparent lids, allotting one said transparent lid on top of the corresponding image sensor chip, and carrying out a packaging process. The manufacturing method of the invention has the advantage of having a simpler process, lower cost, and higher production yield rate. The encapsulation compound arranges on the first surface of the image sensor chip and covers the circumference of the transparent lid to avoid the side light leakage as traditional chip scale package (CSP). Thus, the sensing performance of the wafer level image sensor packaging structure can be enhanced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.