Method for fabricating surrounding-gate silicon nanowire transistor with air sidewalls
US8563370B2 · kind B2 · utility
2Cited by
2References
9Claims
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Key dates
| Filing date | Jul 4, 2011 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Oct 12, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a surrounding-gate silicon nanowire transistor with air sidewalls is provided. The method is compatible with the CMOS process; the introduced air sidewalls can reduce the parasitic capacitance effectively and increase the transient response characteristic of the device, thus being applicable to a high-performance logic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.