Method of manufacturing a semiconductor device
US8563383B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2011 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Oct 4, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0135
Abstract
A method of manufacturing a semiconductor device includes forming a plurality of gate structures including a metal on a substrate having an isolation layer, forming first insulating interlayer patterns covering sidewalls of the gate structures, forming first capping layer patterns and a second capping layer pattern on the gate structures and the first insulating interlayer patterns, the first capping layer patterns covering upper faces of the gate structures, and the second capping layer pattern overlapping the isolation layer, partially removing the first insulating interlayer patterns using the first and the second capping layer patterns as etching masks to form first openings that expose portions of the substrate, forming metal silicide patterns on the portions of the substrate exposed in the forming of the first openings, and forming conductive structures on the metal silicide patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.