Device and methods for small trench patterning
US8564068B2 · kind B2 · utility
3Cited by
0References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 5, 2012 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Jan 15, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures and sidewall spacers, and an etch buffer layer disposed over the sidewall spacers. The etch buffer layer includes an overhang component disposed on the upper portion of the sidewall spacers with an edge that extends laterally. The width between the edges of adjacent overhang components is narrower than the width between adjacent sidewall spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.