Semiconductor arrangement
US8564126B2 · kind B2 · utility
0Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2010 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Dec 21, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12044
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor arrangement, in particular a power semiconductor arrangement, in which a semiconductor having a top side provided with contacts is connected to an electrical connection device formed from a film assembly wherein an underfill is provided between the connection device and the top side of the semiconductor. The underfill has a matrix formed from a preceramic polymer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.