Patent · US Active

Clock tree insertion delay independent interface

US8564337B2 · kind B2 · utility

1Cited by

0References

20Claims

0Family size

Assignee

LSI · US

Inventors

Stefan G. Block · Munich, DE
Herbert Johannes Preuthen · Dorfen, DE
Juergen Dirks · Holzkirchen, DE

Key dates

Filing date	Feb 8, 2011
Grant date	Oct 22, 2013
Priority date	—
Expiry date	Sep 20, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG06F1/08
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Disclosed herein is a multi-clock interface, an integrated circuit and a module thereof having the multi-clock interface and a library having cells corresponding to the above noted circuitry. In one embodiment the multi-clock interface includes: (1) a multi-clock reset synchronizer configured to receive a first external clock signal and a second external clock signal that is a multiple of the first clock signal, the reset synchronizer configured to synchronize a reset of both the first and second external clock signals and based thereon generate a reset release signal and (2) a multi-phase clock generator configured to receive the reset release signal and the second clock signal, the multi-phase clock generator configured to generate multiple clock phases from the second clock signal based on the reset release signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.