Reference clock compensation for fractional-N phase lock loops (PLLs)
US8564342B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 1, 2012 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Apr 21, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1976
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method includes determining a phase difference between a reference clock and a feedback clock in even and odd cycles for a phase lock loop (PLL). The even and odd cycles are alternating clock periods. A delta value based on the phase difference is determined. The method then adjusts a division value used by a divider to generate the feedback clock during the even cycle based on the delta value where the delta value is of a first polarity. Also, the method adjusts the division value used by the divider to generate the feedback clock during the odd cycle based on the delta value where the delta value is of a second polarity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.