Read boost circuit for memory device
US8565030B2 · kind B2 · utility
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6References
11Claims
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Key dates
| Filing date | Sep 22, 2011 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Feb 13, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read boost circuit arranged to boost the voltage difference between a pair of complementary bit lines of a memory device during a read operation, the read boost circuit including: a first transistor adapted to be controlled by the voltage level on a first bit line of the pair of bit lines to couple a second bit line of the pair of bit lines to a first supply voltage; and a second transistor connected directly to ground and adapted to be controlled by the voltage level on the second bit line to couple the first bit line to ground.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.