Configurable accelerated post-write read to manage errors
US8566671B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2012 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Jun 29, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. An error management provides reading and checking the copy after copying to the second portion. If the copy has excessive error bits, it is repeated in a different location either in the second or first portion. The reading and checking of the copy is accelerated by reading only a sample of it. The sample is selected from a subset of the copy having its own ECC, where the sample selected depends on the count of erase-program cycles that a block has experienced, where different count ranges can use different samples.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.