Enhanced analysis of array-based netlists via phase abstraction
US8566764B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2010 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Jun 11, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism is provided for increasing the scalability of transformation-based formal verification solutions through enabling the use of phase abstraction on logic models that include memory arrays. The mechanism manipulates the array to create a plurality of copies of its read and write ports, representing the different modulo time frames. The mechanism converts all write-before-read arrays to read-before-write and adds a bypass path around the array from write ports to read ports to capture any necessary concurrent read and write forwarding. The mechanism uses an additional set of bypass paths to ensure that the proper write data that becomes effectively concurrent through the unfolding inherent in phase abstraction is forwarded to the proper read port. If a given read port is disabled or fetches out-of-bounds data, the mechanism applies randomized data to the read port data output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.