Patent · US Active

Optimized buffer placement based on timing and capacitance assertions

US8566774B2 · kind B2 · utility

1Cited by

1References

10Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Lukas Daellenbach · Altdorf, DE
Elmar Gaugler · Eppelheim, DE
Ralf Richter · Dresden, DE

Key dates

Filing date	Nov 10, 2011
Grant date	Oct 22, 2013
Priority date	—
Expiry date	Apr 11, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method is provided for optimized buffer placement based on timing and capacitance assertions in a functional chip unit including a single source and multiple macros, each having a sink. Placement of the source and macros with the sinks is pre-designed and buffers are placed in branches connecting the source with the multiple sinks. The method includes: calculating an estimated slack for each branch based on cycle reach, calculating a minimum slack for each branch, arranging branches according to the calculated slack to evaluate at least one most critical branch, inserting decoupling buffers in all branches except the most critical branch(es) and placing decoupling buffers close to the source, globally routing the most critical branch(es) and fixing slew conditions within this branch, globally routing at least one subsequent branch as arranged according to the calculated slack and fixing slew conditions within this branch(es), and routing all remaining branches.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.