Semiconductor structure and method of fabrication thereof with mixed metal types

US8569128B2 · kind B2 · utility

Assignee

• SuVolta, Inc. · US

Inventors

• Lucian Shifren · San Jose, US
• Pushkar Ranade · Los Gatos, US
• Sachin R. Sonkusale · Los Gatos, US

Key dates

• Filing date: Dec 3, 2010
• Grant date: Oct 29, 2013
• Expiry date: Aug 8, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/856

Abstract

A semiconductor structure includes a first PMOS transistor element having a gate region with a first gate metal associated with a PMOS work function and a first NMOS transistor element having a gate region with a second metal associated with a NMOS work function. The first PMOS transistor element and the first NMOS transistor element form a first CMOS device. The semiconductor structure also includes a second PMOS transistor that is formed in part by concurrent deposition with the first NMOS transistor element of the second metal associated with a NMOS work function to form a second CMOS device with different operating characteristics than the first CMOS device.