Substrate processing method
US8569176B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2011 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Dec 22, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31138
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a substrate processing method configured to prevent the occurrence of a bowing shape to form a hole of a vertical processing shape on a mask layer, and to secure a remaining layer quantity as the mask layer. The substrate processing method receives a wafer W in which a mask layer and an intermediate layer are stacked on a target layer to be processed in a chamber, generates plasma of processing gas in the chamber, performs an etching process on wafer W using the plasma, thereby forming a pattern shape on the target layer to be processed through the intermediate layer and the mask layer. The etching process etches the mask layer by applying excitation power of 500 W for generating plasma, maintaining processing pressure at 5 mTorr (9.31×10−1 Pa) or less, and maintain temperature of wafer W in the range of −10° C. to −20° C.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.