Method of fabricating gate electrode using a treated hard mask
US8569185B2 · kind B2 · utility
0Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2010 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Feb 21, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0172
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating an integrated device is disclosed. In an embodiment, a hard mask layer with a limited thickness is formed over a gate electrode layer. A treatment is provided to the hard mask layer to make the hard mask layer more resistant to a wet etch solution. Then, a patterning is provided on the treated hard mask layer and the gate electrode to from a gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.