Three-dimensional CMOS circuit on two offset substrates and method for making same

US8569801B2 · kind B2 · utility

Assignee

• COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventor

• Benjamin Vincent · San Francisco, US

Key dates

• Filing date: Aug 10, 2009
• Grant date: Oct 29, 2013
• Expiry date: Jan 13, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D88/01

Abstract

A three-dimensional CMOS circuit having at least a first N-conductivity field-effect transistor and a second P-conductivity field-effect transistor respectively formed on first and second crystalline substrates. The first field-effect transistor is oriented, in the first substrate, with a first secondary crystallographic orientation. The second field-effect transistor is oriented, in the second substrate, with a second secondary crystallographic orientation. The orientations of the first and second transistors form a different angle from the angle formed, in one of the substrates, by the first and second secondary crystallographic directions. The first and second substrates are assembled vertically.