Benjamin Vincent
18Patents
4h-index
15Co-inventors
53Inventor score
Filing activity: Feb 7, 2008 → Sep 4, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9476143B2 | Methods using mask structures for substantially defect-free epitaxial growth | Electricity | 10 | Active |
| US9117777B2 | Methods for manufacturing semiconductor devices | Electricity | 10 | Active |
| US9171904B2 | FinFET device with dual-strained channels and method for manufacturing thereof | Electricity | 9 | Active |
| US9040391B2 | Process for producing localised GeOI structures, obtained by germanium condensation | Electricity | 8 | Active |
| US9029217B1 | Band engineered semiconductor device and method for manufacturing thereof | Electricity | 4 | Active |
| US9368498B2 | FinFET device with dual-strained channels and method for manufacturing thereof | Electricity | 4 | Active |
| US9263528B2 | Method for producing strained Ge fin structures | Electricity | 3 | Active |
| US11158368B2 | Static random-access memory cell design | Electricity | 2 | Active |
| US8501596B2 | Method for fabricating a micro-electronic device equipped with semi-conductor zones on an insulator with a horizontal GE concentration gradient | Electricity | 1 | Active |
| US9831374B2 | Photodetector with tapered waveguide structure | Emerging Cross-Sectional Technologies | 1 | Active |
| US7989327B2 | Manufacturing method for a semi-conductor on insulator substrate comprising a localised Ge enriched step | Electricity | 1 | Active |
| US8247313B2 | Method for preparing a germanium layer from a silicon-germanium-on-isolator substrate | Electricity | 1 | Active |
| US8963225B2 | Band engineered semiconductor device and method for manufacturing thereof | Electricity | 1 | Active |
| US8530339B2 | Method for direct deposition of a germanium layer | Electricity | 0 | Active |
| US8709918B2 | Method for selective deposition of a semiconductor material | Electricity | 0 | Active |
| US10340139B2 | Methods and mask structures for substantially defect-free epitaxial growth | Electricity | 0 | Active |
| US9263263B2 | Method for selective growth of highly doped group IV—Sn semiconductor materials | Electricity | 0 | Active |
| US8569801B2 | Three-dimensional CMOS circuit on two offset substrates and method for making same | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.