Pad design for circuit under pad in semiconductor devices
US8569856B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2011 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Mar 24, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of a semiconductor device that includes a semiconductor substrate and a cavity disposed in the semiconductor substrate that extends at least from a first side of the semiconductor substrate to a second side of the semiconductor substrate. The semiconductor device also includes an insulation layer disposed over the first side of the semiconductor substrate and coating sidewalls of the cavity. A conductive layer including a bonding pad is disposed over the insulation layer. The conductive layer extends into the cavity and connects to a metal stack disposed below the second side of the semiconductor substrate. A through silicon via pad is disposed below the second side of the semiconductor substrate and connected to the metal stack. The through silicon via pad is position to accept a through silicon via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.