Wei Zheng
148Patents
17h-index
291Co-inventors
89Inventor score
Filing activity: Dec 20, 2001 → Apr 8, 2025
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9690936B1 | Multistage system and method for analyzing obfuscated content for malware | Physics | 175 | Active |
| US6912163B2 | Memory device having high work function gate and method of erasing same | Electricity | 113 | Expired |
| USD798807S1 | Charger | General | 96 | Active |
| US7365389B1 | Memory cell having enhanced high-K dielectric | Electricity | 76 | Expired |
| US6782350B1 | Method and apparatus for managing resources | Physics | 60 | Expired |
| US6639271B1 | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same | Electricity | 57 | Expired |
| US6630383B1 | Bi-layer floating gate for improved work function between floating gate and a high-K dielectric layer | Electricity | 46 | Expired |
| US9386088B2 | Accelerating service processing using fast path TCP | Electricity | 46 | Active |
| US6744675B1 | Program algorithm including soft erase for SONOS memory device | Physics | 36 | Expired |
| US6754105B1 | Trench side wall charge trapping dielectric flash memory device | Electricity | 36 | Expired |
| US8338856B2 | Backside illuminated image sensor with stressed film | Electricity | 31 | Active |
| US7188170B1 | System for managing resources | Physics | 28 | Expired |
| US6885590B1 | Memory device having A P+ gate and thin bottom oxide and method of erasing same | Electricity | 26 | Expired |
| US6693321B1 | Replacing layers of an intergate dielectric layer with high-K material for improved scalability | Electricity | 24 | Expired |
| US10657251B1 | Multistage system and method for analyzing obfuscated content for malware | Physics | 23 | Active |
| US9698185B2 | Partial buried channel transfer device for image sensors | Electricity | 22 | Active |
| US8364682B1 | Identifier mapping from joined data | Physics | 18 | Active |
| US8424005B2 | System and method for time-aware run-time to guarantee time | Physics | 15 | Active |
| US8071429B1 | Wafer dicing using scribe line etch | Electricity | 15 | Active |
| US8233066B2 | Image sensor with improved black level calibration | Electricity | 14 | Active |
| US6861307B2 | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same | Electricity | 12 | Expired |
| US6897110B1 | Method of protecting a memory array from charge damage during fabrication | Electricity | 10 | Expired |
| US8569856B2 | Pad design for circuit under pad in semiconductor devices | Electricity | 10 | Active |
| US7071538B1 | One stack with steam oxide for charge retention | Electricity | 10 | Expired |
| US6735123B1 | High density dual bit flash memory cell with non planar structure | Emerging Cross-Sectional Technologies | 8 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.