PVT-free calibration circuit for TDC resolution in ADPLL
US8570082B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2013 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Feb 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to an all digital phase locked loop (APDLL) that can account for variations in PVT conditions, and a related method of formation. In some embodiments, the ADPLL has a controllable time-to-digital converter (TDC) having a plurality of variable delay elements. The controllable TDC is determines a phase difference between a frequency reference signal and a local oscillator clock signal and to generate a phase error therefrom. A digitally controlled oscillator (DCO) varies a phase of the local oscillator clock signal based upon the phase error. A calibration unit determines an effect of variations in PVT (process, voltage, and temperature) conditions based upon the phase error and to generate a TDC tuning word that adjusts a delay introduced by one or more of the plurality of variable delay elements to account for the variations in PVT conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.