Differential ROM
US8570784B2 · kind B2 · utility
4Cited by
10References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 28, 2011 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Oct 26, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A differential read only memory array includes a differential sense amplifier coupled to first and second bit lines. A first bit cell is coupled to a first word line and to the first and second bit lines. The at least one bit cell includes a first transistor having a gate coupled to the first word line, a drain coupled to the first bit line, and a source coupled to a first power supply line. A second transistor has a gate coupled to the first word line. A source and a drain of the second transistor are either both connected to the second bit line or both unconnected to the second bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.