Circuit and method of word line suppression
US8570791B2 · kind B2 · utility
20Cited by
2References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 5, 2011 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Mar 6, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A word line driver circuit for providing a suppressed word line voltage includes a switch configured to selectively load a word line to a suppressed word line voltage node and a word line charging circuit coupled between a high power supply node and the suppressed word line voltage node. The word line charging circuit includes a first transistor device responsive to a control pulse for charging the suppressed word line voltage node to a suppressed word line voltage and a second transistor device for maintaining the suppressed word line voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.