Flash memory devices and systems
US8570809B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2011 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Apr 6, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/69
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Flash memory devices and systems are provided. One flash memory device includes an n-channel metal oxide semiconductor field-effect transistor (nMOSFET), a silicon-oxide-nitride-oxide silicon (SONOS) transistor coupled to the nMOSFET, and an isolated p-well coupled to the nMOSFET and the SONOS transistor. A flash memory system includes an array of memory devices divided into a plurality of paired sectors, a global bit line (GBL) configured to provide high voltage to each respective sector during erase and program operations coupled to each of the plurality of sectors, and a plurality of sense amplifiers coupled between a respective pair of sectors. Methods for operating a flash memory are also provided. One method includes providing high voltage, via the GBL, to the paired sectors during erase and program operations and providing low voltage, via a local bit line, to each memory device during read operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.