Memory apparatus and testing method thereof
US8572444B2 · kind B2 · utility
4Cited by
10References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2010 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Dec 11, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory apparatus and a related testing method are provided in the present invention. The memory apparatus includes a memory and a testing module. The testing module includes an error recording unit for recording corresponding addresses of bit errors occurred in the memory. The testing module determines whether the memory has multi-bit error according to the addresses recorded in the error recording unit. The memory is an ECC memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.