Method and apparatus for performing path-level skew optimization and analysis for a logic design
US8572530B1 · kind B1 · utility
4Cited by
33References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2010 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Dec 6, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for designing a system including optimizing path-level skew in the system and analyzing path-level skew in the system. Other embodiments are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.