Semiconductor devices having e-fuse structures and methods of fabricating the same
US8574975B2 · kind B2 · utility
5Cited by
2References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 5, 2013 |
| Grant date | Nov 5, 2013 |
| Priority date | — |
| Expiry date | Mar 5, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes: an e-fuse gate, a floating pattern between the e-fuse gate and an e-fuse active portion, a blocking dielectric pattern between the floating pattern and the e-fuse gate, and an e-fuse dielectric layer between the floating pattern and the e-fuse active portion. The floating pattern includes a first portion between the e-fuse gate and the e-fuse active portion and a pair of second portions extended upward along both sidewalls of the e-fuse gate from both edges of the first portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.