Group III-V semiconductor device with strain-relieving interlayers
US8575660B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2009 |
| Grant date | Nov 5, 2013 |
| Priority date | — |
| Expiry date | Nov 10, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to one exemplary embodiment, a group III-V semiconductor device includes at least one transition layer situated over a substrate. The group III-V semiconductor device further includes a first strain-relieving interlayer situated over the at least one transition layer and a second strain-relieving interlayer situated over the first strain-relieving interlayer. The group III-V semiconductor device further includes a first group III-V semiconductor body situated over the second strain-relieving interlayer. The first and second strain-relieving interlayers comprise different semiconductor materials so as to reduce a strain in the first group III-V semiconductor body. The second strain-relieving interlayer can be substantially thinner than the first strain-relieving interlayer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.