Systems and methods including features of power supply noise reduction and/or power-saving for high speed delay lines
US8575982B1 · kind B1 · utility
27Cited by
9References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2013 |
| Grant date | Nov 5, 2013 |
| Priority date | — |
| Expiry date | Mar 8, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to systems and methods of noise reduction and/or power saving. According to one or more illustrative implementations, for example, innovations consistent with delay lines in clock/timing circuits such as Delay-Lock-Loop (DLL) and/or Duty Cycle Correction (DCC) circuits are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.