Calibration method and circuit
US8576102B2 · kind B2 · utility
2Cited by
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21Claims
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Key dates
| Filing date | Dec 5, 2011 |
| Grant date | Nov 5, 2013 |
| Priority date | — |
| Expiry date | Dec 5, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/46
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog input signal is sampled, and the sampled analog input signal is converted to a digital value. A calibration value is also sampled, and a single bit of an N bit offset value is calculated from the sampled calibration value. The sampling operations are alternatively performed so that one bit of the offset value is generated for each generated digital value. For example, the process is repeated N times to calculate all N bits of the offset value while generating N digital values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.