Multi-wafer 3D CAM cell
US8576599B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2012 |
| Grant date | Nov 5, 2013 |
| Priority date | — |
| Expiry date | Mar 11, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-wafer CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-wafer CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the inventive CAM cell can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-wafer CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.